Digital I/O sampling frequency question.
 

Our team is attempting to use a linear magnetic sensor to create an index pulse when passing a magnet. This pulse signal connects to the digital sidecar, digital I/O. Using Labview, we are monitoring (displaying) these pulses using the "Simple Digital input" VI. When we compare the pulses produced by the chip sensor using an O'scope with the Raw value of the Dig I/O pin in Labview, they are very different. The O'scope is perfectly consistant pulse periods and the Labview display frequently has gaps where 2, 3 or more pulses should be.

Our conclusion is that the Dig I/O is not properly sampling the I/O port and missing some pulses. Is this a good conclusion and if so, can we adjust settings in Labview or the CRIO to correct this?

Re: Digital I/O sampling frequency question.
 

If you are trying to find the time between quick pulses, don't use a digital IO object, use a counter. You should leave the sensor connected the way it is now, and just use the period terminal on the counter vi in LV, or in c/java, use counter.getPeriod(). The counter uses the FPGA to count the signal really quickly just like an encoder and we've had success using this to measure our shooter's wheel speed.

Re: Digital I/O sampling frequency question.
 

http://www.sal.wisc.edu/PFIS/docs/rs...403-manual.pdf

So you need to understand the difference between the cRIO Module & FPGA and the software layer on top of it.

The cRIO module can detect changes about every 1 microsecond, so unless you're getting one million pulses per second, you're probably not saturating the hardware.

What I expect you're doing is just reading the "current" value of the I/O pin in software, which is probably running every few milliseconds. In that case, if you're getting >100 or >1000 pulses per second (hard to say for sure without knowing the execution speed of your program) you may miss some transitions.

What you could do is set one of the cRIO's hardware counters to read off an I/O pin. I can't remember how to set this up yourself, but the encoder class does this automatically. Essentially, the FPGA counts things in hardware, and the software layer comes along every once in a while and asks "how many pulses have you recorded?" The hardware delivers the number and then resets the counter.