Re: Failed attempt to explain JAG linearity
 

On the subject of H bridge controllers, it might be beneficial to look at this data sheet. It's for an Allegro automotive H bridge driver chip. In the data sheet it gives all methods of driving the external FET's, but stops short of explaining the advantages for the different methods.
http://www.allegromicro.com/en/Produ.../3941/3941.pdf
It's similar to the Referenced power point but goes further.Starting on page 13 all the drive methods that have been mentioned are shown and the last method where both lower Fets are turned on. It's referred to as slow decay as compared to fast decay with the diode in the recirculating loop. Slow decay adds the complexity of high side turn off and low side turn on. The Fairchild driver has shoot through protection but will not work in this design because the chip enable is being used for PWM control.
It was mentioned in this thread that the model was just like a DC -DC switching power supply with the 2 half brides stuck together. If you look at the data sheets for the jag Fairchid half bridge driver and the FETs, it also looks like the Luminar Micro designers had this view also. They chose a driver that was designed for a switching power supply. The FETS were chosen for low gate charge, fast on off and logic level for even easier drive. Perfect for a DC switcher because the half bridge is constantly switching Hi low hi low. The low side body diode only see's current for a very short time during the dead time while the low side fet is turning on. A DC switcher also has a large capacitance compared to the inductor in the circuit. For a motor the capacitance compared to the motor inductance is so small that it is essentially ignored. After following this thread I'm starting to see the differences between a half bridge switcher and a h-bridge motor driver.
What sticks out to me is that the thread has come to focus on the switch off and recirculation. In particular the low side body diode. In the victor how many times a second does the high side body diode see an avalanche condition? With the jag how many times per second does the low side body diode see an avalanche condition? How much power do they dissipate. Then, I know this model has been simplified and it's looking at averages, but what about the switch off transient? How big is it? Does it affect other parts? How much power is being dissipated by the diode in the recirculation?

After following this thread I have a hunch that historically this is what happened. IFI had the 883 design and it was fine in the beginning. With a frequency of 2000 and smaller drive motors, the non-linearity and power dissipation were not an issue. Then things started to change. First was going in the Tim Allen "More Power" direction. IFI saw the large drill motors and CIM motors in the future. They could see issues with the 883 design. They were faced with having to invest in a total redesign to handle the future needs. Instead of total redesigning the controller, somebody had the great idea of " hey lets just slow the 883 down and call it the 884". At the lower PWM frequency the same design could handle the CIMS except that irritating non-linearity issue that is the focus of this thread. Then comes Luminary Micros and the powerful micro controller. They jump in and give us a fantastic controller with a whole bunch of capability that will carry FIRST forward for years to come. Plus they gave us a linear controller. However the switching transience and power dissipation issues that IFI side stepped are back. Now Luminary Micros this year has proven by actions to be a primo grade A FIRST supplier. IF I'm right the jag needs a little redesign for 2010. Can LM address what IFI side stepped?

I know I went off topic and made some subjective statements, But this thread caused them. I'm not wearing the ceramic protective so please keep the temp down. Ok here I go I'm hitting the submit button.

Re: Failed attempt to explain JAG linearity
 

Some of the wave forms on the scope lead me to believe this but the Hbridge.c tells us that only one low side fet is on under normal operating conditions. If charging with A/D on then the off has only D on when A is switched off. The B (low side) is not switched on. So no dead time is necessary.

I have been thinking about this analogy for a few weeks now and I think it is an exact one. You can replace Vemf in the circuit with a large capacitor C = Izz/ke/kt (apporx 0.7 farads). Izz is the motor inertia load, ke and kt are the standard motor constants. This C relates the dVemf/dt to the difference between the inductor ( L ) current less a load current .

In a dc switching model the load is generally a resistor which draws a load current of Vout/Rload. In the motor model, the load current is nonlinear due to coulomb friction but there is probably also some proportional load due to viscous friction. The viscous current would be modeled with just a Rload across C.

So if you draw the circuit, it looks exactly like a DC switching supply except it does't have the regulator feedback. When the encoder speed or Vemf is fed back in an error loop then we have a complete DC switching regulator.

I view the motor as a series RLC with a diode across it and a load current source bleeding off the current from the L. The load current source would = - i_free*sign(Vemf). The RLC behaves as a RC circuit for low frequencies with first order time constant tau = RC . For high frequencies, we have the RL approximation, since the C looks like a battery with voltage Vemf and we have the switching current model. My simulation of course captures both these aspects in one model since I include the motor torque equation and inertia effects.

If you have access to a spice simulator, you can generate the transients equivalent to my sim. I had a little trouble with CircuitMaker because it kept coming up with a sim step too small error but a professional spice sim would probably handle it. If anyone wants to try it, I'll work with them to get the model parameters set.



I could be dead wrong, but I don't see yet why the diodes need to operate in an avalanche condition. In the JAG normal mode, they would conduct during the off phase in a normal manner and the power would be similar to what I spoke of in my last post. You can make a good guess by assuming the current to be the average current running through 1.25v and multiplied by 1-duty. When the motor is loaded, the currents are very high but the 1-duty would scale the power dissipation.

Lets say we are in stall so Vemf = 0. The avg current is approx = 12v/R*duty. The power = 1.25*12/.1*duty*(1-duty)
= 150*(duty-duty*duty). The peak power would be at duty=.5 -> 150/4 or about 40 watts. So things things could heat up in a hurry if my thought process is correct. Of course we could guess...just look at the ratings of the FET diodes and the capability of the JAG design to dissipate heat. This I haven't done.

Re: Failed attempt to explain JAG linearity
 

Well I got CircuitMaker to work finally. I just picked a JFET that would do something. The actual spice models for the JAG would be closer. The Cm capacitance =7.5 farads for the assumed inertia load. I had used .75 to speed the motor response up in earlier studies.

I attached a Jpeg picture of ckt and a CircuitMaker model as a .C file. If you have CircuitMaker, download file and change .c to .ckt to run.

So..Maybe you ckt guys can whip up a better model of the FET's and try your luck with a spice simulator program.

Re: Failed attempt to explain JAG linearity
 

Chris,
I am woefully low on time but I did want to add the the diodes in the FETs are avalanche diodes by design.

Re: Failed attempt to explain JAG linearity
 

Yes, I'm with you there re the high frequency avalanche conditions existing due to parasitic inductances. Models can get real complicated with parallel FETs and I leave this area to the experts.

I assumed that Gdeaver was referring to low frequency recirculation currents of the main inductance not the parasitic inductances. So I hope my comments were accurate in that regard.

Re: Failed attempt to explain JAG linearity
 

Chris,
I thought Gary was referring to the same thing as me. The FET data sheet lists the diodes as avalanche devices.

Re: Failed attempt to explain JAG linearity
 

I've seen the data sheets and fully agree that the diodes are avalanche devices. They will breakdown at 30 v.

I am maintaining that the avalanche condition will only be caused by the parasitic inductances since that is their only current path. These recirculation's are characterized by the higher frequency type waveforms (dying out in less than 10usec). The lower frequency (pwm period) currents associated with the motor inductance will not cause a reverse breakdown since these currents have a lower voltage path of a fwd biased diode in the base FET.