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Originally Posted by apalrd
Is there any reason why it worked fine last year (cRio image 20) but doesn't work this year (tested cRio image 25)?
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Because the FPGA image is different than last year.
Quote:
Originally Posted by apalrd
Also - Will it care if I allocate the dummy encoders on slot 6, if I don't actually have a DIO module on slot 6?
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No... it won't care. And neither will you because you aren't using them.
Quote:
Originally Posted by apalrd
Also again - Is it that every other encoder works, or every other encoder created works? If I were to edit the VI that assigns counters (or encoders), and told it to only assign the odd or even counters (or encoders), would that fix things?
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Based on reports, it is every other encoder... so if you change the VI to assign only even encoders, then they should all work. I have not actually tried this approach so I can't guarantee that it will work, but it sounds reasonable.