Quote:
Originally Posted by ayeckley
Writing fixed timebase rate codes (as opposed to interrupt-triggered ones)gets complicated, especially at low rates when there are relatively few ticks per loop (aka discretization error). Looks like we'll have to add a second DSC and DIO module to our already-completed electronics board be able to use closed-loop control for our drive motors since all of our DIO channels are used (assuming I'm understanding the "every other channel" workaround correctly).  |
I don't think you are reading my post very carefully. The issue has nothing to do with the I/O on the side car... only the decoding engines in the FPGA. Adding a side car will not help. You simply need to allocate the encoder or counter objects that have functioning timer modules (rate calculators). I have provided VIs that will do just that. If you use the VIs I posted, you don't need to call anything twice or whatever other things people have been saying to do. Just use the API as it was intended and it should work for you.
Quote:
Originally Posted by ayeckley
Unless: Joe - any chance someone at NI could provide some reference code based on an interrupt-driven approach instead of a timed loop approach? We just don't have enough time between now and ship date to write and test our own version.
|
I don't have that ready to go, so I would be trying to make sure it was perfect too, and with just a few days left, it's probably not worth while and wouldn't be perfect. Perhaps some other team has implemented it this way and wants to share.
The work around above allows you to read up to 6 encoders with the FPGA calculating rate for you. Only if you need more than 6, do I recommend writing your own rate algorithm.
-Joe