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Unread 21-03-2011, 13:48
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Re: Partial Jag failure?

Quote:
Originally Posted by Al Skierkiewicz View Post
In the Tan Jag there is no feedback from the output terminals so the zero volt condition must be derived mathematically from internals.
I was just digging in the source code for the BDC (not the newer BDC24...the black Jaguar).

They have a file in that firmware: adc_ctrl.c

In that file:

Quote:
//
// Configure the GPIOs used with the analog inputs.
//
GPIOPinTypeADC(ADC_POSITION_PORT, ADC_POSITION_PIN);
GPIOPinTypeADC(ADC_CURRENT_PORT, ADC_CURRENT_PIN);
GPIOPinTypeADC(ADC_VBUS_PORT, ADC_VBUS_PIN);
GPIOPinTypeADC(ADC_VBOOTA_PORT, ADC_VBOOTA_PIN);
GPIOPinTypeADC(ADC_VBOOTB_PORT, ADC_VBOOTB_PIN);
Then later down the source code...

Quote:
//************************************************** ***************************
//
// This function returns the current bus voltage, specified as an unsigned 8.8
// fixed-point value that represents the voltage.
//
//************************************************** ***************************
unsigned long
ADCVBusGet(void)
{
//
// Convert the ADC reading into a voltage and return it.
//
return(ADC_TO_VBUS(g_pusADCData[VBUS]));
}
This got me thinking....I know in the black Jaguar you can clearly see in the schematic where the voltage divider for the VBus measurement is.

However, it appears in the older schematic they hid this divider in the schematic section for the power regulation.

Look right next to C15 on the schematic...for the VSENSE tag.
It's on the second page of schematics in the user manual and it's between the great big tag for "+12V POWER IN" and the 5V power regulation.

In pins.h they define:
Quote:
#define ADC_VBUS_PORT GPIO_PORTE_BASE
#define ADC_VBUS_PIN GPIO_PIN_3
#define ADC_VBUS_CH ADC_CTL_CH0
I'm pretty sure that in both cases (the old and the new Jaguar) this means that they aren't measuring at the output terminals...but they seem to be measuring the same thing.

Last edited by Al Skierkiewicz : 21-03-2011 at 15:05.
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