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Unread 12-07-2011, 17:20
James Critchley James Critchley is offline
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Re: Cartesian to angle

Fantastic!

I though you were going to post the trig logic to do all of the calculations. "atan2" is certainly the way to go, transforming coordinates before using it is great.

I need to look at a clock again... right hand rule = CCW!!! See my earlier post.


From a readability perspective, consider defining a macro statement such that.

angle = HEADING(0,0);



atan2(0,0) is undefined in the standard. So for cross platform use, you should check for this as an arbitrary compiler can throw an exception.

if y == 0.0 then y = 1e-8.

Assuming you aren't working with nano-bots this will do nicely and leave your (0,0) point at 0. Unfortunately this adds a comparison operation which, as implied here, are commonly the most costly operations and what you are trying to avoid. This is a prety good arguement for changing the standard.


I did some reading, and as Ether pointed out, ALL recent Intel chips define (0,0) as 0 and this is on the chip and part of the FPU. If you use a look-up table, you need an unbounded (or large) 2D table in x and y... You can manage this by normalization or conversion to a one dimensional problem but atan2 solves it right there in the silicon. There are a host of other issues with the look-up table but the one that strikes me is the effort associated with continually moving a table back and forth through the layers of cache on the chip (Cache is MUCH smaller than RAM). It's not a good option and should not be faster (coding or execution with other intensive code in the loop) or portable to higher resolution applications. In the interest of exhausting all alternatives, the look-up table certainly is "out of the box" and I like it. Keep up the good work!

With the Intel FPU, most modern PC's and Macs will get (0,0) = 0 "right" provided the compiler actually accesses the FPU directly for this calculation (that would be most compilers including gcc). But what does the cRIO do? Is the FPGA intel based? Looks like "Xilinx Virtex" is a custom processor for FPGA? So you need documentation of a firm commitment to define the result as 0, or you need to test and a re-test every time the chip is upgraded which could happen without a "model" change to cRIO.