[Jared Russell]

Originally Posted by jhersh

Floating point operations are not done in the FPGA on cRIO, they are done in the PPC core's FPU. You can look at the details for it here: http://cache.freescale.com/files/32b...e300coreRM.pdf

Edit: FP instructions are in section 3.2.4.2 (pg 119).

Joe,

Thanks for the link to this document! For those interested, the latency (in cycles) of each instruction on the PPC is listed starting on page 300 (section 7.7). Hopefully this can be a tool to help settle arguments in the future.