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Unread 14-07-2011, 10:16
Greg McKaskle Greg McKaskle is offline
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Re: Cartesian to angle

I'm by no means an FPGA expert, but I'll attempt to quench some of the curiosity.

FPGA stands for "field programmable gate array". NI uses it in our RIO platform of products, which stands for "reconfigurable I/O". Both the FP and R in the acronym attempt to convey that this piece of HW is user-definable, configurable, perhaps even programmable -- given that you have the tools and the know-how. The GA in the acronym declares that the elements being configured are discrete logic gates, as opposed to analog op-amps or other electronic elements. In the RIO family of products, the FPGA is used for highly deterministic triggers, filters, and timing of I/O pins on the modules. It is connected to the processor bus and I/O configuration and values can be accessed by the traditional CPU also running flexible user code.

Rather than think of the FPGA as a processor, think of it as a user-configurable digital logic circuit board, something like a very very dense protoboard which is populated with NAND gates. As with a protoboard, you build the circuit by wiring between the logic elements to produce the circuit you need. Fortunately, as with the circuit board, your tools allow you to use higher level circuit elements than just NAND gates. You can declare registers, flip-flops, adders, etc. Unlike the attached protoboard image, you cannot include capacitors or other analog circuit elements.
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For FRC, the circuit produces the pulses for lots of PWMs, clocks I2C pins, decodes quadrature signals, accumulate the values returned from rate gyros, etc. The "circuit" could instead have been designed and "burned" into an ASIC I/O chip that was connected to the PPC's PCI bus. I suppose FIRST could alternately send a tub of TTL level logic and have you build your own I/O circuit on a very large protoboard. Instead, this circuit was programmed in the LV FPGA tools -- other FPGA tools could have been used. It is then compiled using the XILINX tools into an FPGA image, and "burned" by telling the RIO driver to upload the file to the FPGA chip.

Rather than dig deeper into what an FPGA is, or why the cRIO uses one in addition to running a realtime OS on a traditional CPU, let me reference an article on NI's website. LINK

FPGAs are a relatively new technology, but are already embedded in many devices where low-jitter, high performance, and flexible field-updates are required. The XILINX site can give examples other than the cRIO and its integrated I/O usage.

Greg McKaskle

Last edited by Greg McKaskle : 14-07-2011 at 10:24. Reason: spelling and grammar