Quote:
Originally Posted by Joe Ross
On the NI FIRST community, Joe Hershberger said the limit is 39,987 counts per second. https://decibel.ni.com/content/message/12523 All of this is handled by the FPGA, so there is no additional processor load as you increase the count rate.
Joe made one important caveat, that there is a perfect 90 degree phase relationship between the signals from the encoder. This isn't true with a real world encoder. I would leave 50-100% margin and only use a range of 30-20k counts per second. |
Since you don't need direction for this application, if you used just one channel from the encoder (physically disabled the other channel in the cable), would the FPGA processing still work? And would that help make the allowable speed higher?