[RyanN]

It's funny you mention funny error messages...

Last semester, I was in my Digital System Design class (DSD), where we have to write Verilog code for a Spartan 3E FPGA board, the Basys2.

The software that we use is called Xilinx.

(Hopefully some of this is somewhat familiar to you guys, you use a Spartan 6 in the cRIO, and you have some Xilinx tools installed if you installed all of the FIRST software)

Anyway, a lot of the warnings/errors thrown when err... building (Really called Synthesizing, Translate, Map, and Place & Route) are poorly written.

Such as:
"WARNING:Route:455 - CLK Net:i_clkdiv/clkout may have excessive skew because"

Because... the ultimate excuse behind anything.

I know one of my other friends got an error along the lines of "ERROR: This process has run into an error because there was an error."