Quote:
Originally Posted by Ether
Are you saying the FPGA running the FRC firmware cannot be configured to count pulses on one channel and make that count available to the CPU? Or just that the high-level encoder class is not designed to do that?
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I am not sure if it can or cannot. After all, the FPGA is programmable, the firmware can configure it anyway it could. My understanding is that the FPGA implements the counter for the encoders and the Encoder module in the WPI library is expecting both channel A and B. There is no method in the Encoder module that accepts only one channel. So I am making a speculation that it does not support one channel. However, it is probably possible to implement a software counter. But I don't know the innards of the FPGA enough to be able to do that.