Quote:
Originally Posted by Patrick Chiang
the loop would be to run until the FPGA time is equals or greater than 125400 ms. And then, it stops running because the conditional is no longer true.
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this is called "busy waiting" or "spinning" and it chews up CPU time.
not the best way to do things.
http://en.wikipedia.org/wiki/Busy_waiting
http://citeseerx.ist.psu.edu/viewdoc...=rep1&type=pdf