[Alan Anderson]

I have no real insight into the FPGA code, so this is just a guess based on the reported behavior. It could be completely wrong.

When you Start an encoder, it presets some internal registers. The FPGA is doing quick sampling of the encoder signals, going through something like a state machine to do the up/down counting. If one of the channels is high while the other is low, the first sample will end up making the FPGA think it just counted up one tick. If you Start on a regular basis, it will end up counting that fast.

The answer is, of course, not to do that.

(The true solution might be to search for, find, and fix a possible bug in the FPGA code. Or it might be for someone at NI to slap me for presuming to have anything useful to say on the subject.)