[Greg McKaskle]

Does this happen because your control loop isn't keeping up with the DMA rate? If you are consuming a 100Hz stream with a 10ms delay, you are approximately keeping up, but each little delay in the FPGA producer adds a little bit of extra data to the buffer that the consumer doesn't get to. This would probably improve enough if you will switch from a regular loop to a Timed Loop. The timed loop runs on a different scheduler and at an elevated priority. The other solution is to run the consumer loop until the buffer is empty, take the latest data from the buffer, etc.

Greg McKaskle