Just to add to this body of knowledge, for any of you still following this discussion:
Can anyone guess why the Jag designer chose to use the Low side of the H-bridge to close the inductive current loop vs. the top side?
Follow on Ether's thumbnail diagram LEFT (two posts up).
Using top loop to short the inductive current:
In the PWM-High cycle Q1 and Q4 are on.
When PWM=Low, we switch off Q4, and the voltage on the right motor terminal spikes to 12.6V. Then the Intrinsic Diode of Q3 starts to conduct and we are in the "Dead Time". After 2us, the Jag switches on Q4. The voltage needed on the the Gate needs to be 22V (12V Battery+10V VGS)
In the actual case of using the Low-side shunt we just need +10V on the Gate of Q2. (We still need +22V on the gate of Q1.)
So one might think it odd that we need 22V in a 12V battery powered circuit. Well the genius of this lies in the H-Bridge driver chip:
http://www.allegromicro.com/en/Produ.../4940/4940.pdf
This chip has an on-board power supply, and also a mechanism to “float” the driver stages of the High-side Mosfet drivers so they float on the corresponding Mosfet Source pin voltage whatever that is 0, or 12V. That way they can always drive the Gate at 10V above the Source. The Gate voltage to drive Q1 is also +22V.
The real issue however is that the H-Bridge driver's internal power supply mechanism uses Bootstrap Capacitors to ensure sufficient voltage to drive the high-side gates. The capacitor is recharges only when the Motor Terminal is at 0V. Therefore there needs to be periodic dips to 0V for each of the Motor terminals. The Jag document addresses this, in:
http://www.ti.com/lit/ug/spmu130c/spmu130c.pdf
“One restriction with the boot-strap capacitor method is that the capacitor voltage will decay to an unacceptable level unless a low-side MOSFET is periodically switched on. This state only occurs when the motor is running full-forward or full-reverse.”
This would occur also at any power level if the High-side were used for the inductor current shunting. The driver chip will sense this and temporarily switch off the top Mosfet, and switch on the bottom Mosfet to get the Motor terminal to 0V and recharge the bootstrap capacitor.
See the simulation below for the two mechanisms. The 3 traces are I(L) current through our stalled CIM (at 50% PWM), Blue V – Voltage on the left Motor Terminal, Red V – Voltage on the right Motor Terminal. You can see that when the High-side is used for the inductor current, the voltage on the left Motor Terminal never goes below 11.2V and would not keep recharging the left Bootstrap capacitor.
http://i.imgur.com/2pZ6X.png
(The simulation does not use the forced-ON of the Mosfet to prevent the Diode current from being the limiting thermal parameter.)
FYI, the 2us Dead_Time is defined by an external resistor on the H-Bridge driver chip (R34) and is used twice per PWM cycle, so our Power calcs earlier still hold.
I think this horse is truly dead
