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Re: I2C implementation on the cRIO
Joe Hershberger can give you better details that I can, but I'll take a whack at it until he finds this thread.
The short of it is that the I2C implementation is limited by the speed of the digital IO and the bi-directional nature of the protocol.
A 100% compliant implementation requires the master to check whether the slave is holding the bus low on every single bit. Checking for clock stretching like this takes a few extra IO cycles, and is usually unnecessary. For speed, it is by default omitted. Compatibility mode checks for stretching in more places.
What I'm not clear on is where stretching is checked in which mode.
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