There are many good explanations of the PWM communication protocol on the web and on these forums. I suggest starting there before moving forward.
Quote:
Originally Posted by Michael Hill
It seems like that limitation should be lifted when using the cRIO board, which appears to be a rebranded NI-9076 board running the Xilinx Spartan-6 LX45 FPGA, which looks like it is a 16-bit controller, and that seems to usually be the "bit chokepoint" when trying to generate a pwm signal.....This isn't a limitation by the victors or jags are they? I haven't taken apart a Victor, but it looks like there are just a bunch of LM317s in there. It looks like there's a large capacitor. Now if you just have an RC filter in there (which explains the large cap), there should be no problem accepting a higher resolution PWM signal. I haven't tried this. Would that be possible to do? Sometimes 8-bits just isn't enough.
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There are several fundamental misunderstandings in this section.
The FPGA is not a 16 bit controller.
The big capacitor is to handle the large current spikes when the bridge is switched.
These PWM signals are not decoded by an RC filter.
8 real bits certainly is enough for FRC.
The "bit chokepoint" in PWM is fundamentally limited by the IO update rate and the combined accuracy of the oscillators in sender and receiver.