Quote:
Originally Posted by EricVanWyk
There are many good explanations of the PWM communication protocol on the web and on these forums. I suggest starting there before moving forward.
There are several fundamental misunderstandings in this section.
The FPGA is not a 16 bit controller.
The big capacitor is to handle the large current spikes when the bridge is switched.
These PWM signals are not decoded by an RC filter.
8 real bits certainly is enough for FRC.
The "bit chokepoint" in PWM is fundamentally limited by the IO update rate and the combined accuracy of the oscillators in sender and receiver.
|
I'd disagree that 8 bits is enough, but at any rate, how are the PWM signals decoded?