[Greg McKaskle]

Adding in ...

The executing FPGA is a circuit constructed using a special form of a LabVIEW diagram. The diagram is compiled into VHDL, and then compiled into a bit mask image.

The FPGA sits between the PPC and the modular backplane. All I/O requests on the backplane go through it or originate from it. The FPGA synthesizes as many registers as specified, and the registers hold setpoints and outputs that can be peeked and poked by the C or LV code running on the PPC.

The FPGA can be imaged in a few seconds, and in fact is imaged several times during boot up. The first one reads in all of the calibration values stored in the modules and stores them in RAM. The second no longer needs the circuitry to access those values, and therefore has room for more functionality.

So, what does the second FPGA image do? For analog, it clocks the module values into registers or into a DMA buffer. It can average, oversample, and level trigger based on the value. It implements a scan list to allow for different scan rates on different channels in the module.

For digital, it determines whether a given line should be an in or out. For ins, it can store them in registers, DMA, it can trigger, count, and quad decode them. For outs, it produces PWMs and pulses of various forms.

The FPGA has a crossbar that gates all outputs and that is controlled by a watchdog counter that must be fed in order to keep the gate open. It can also raise interrupts on the PPC.

The FPGA does could do floating point math, but it would take lots of gates, so it uses integers or fixed point numbers everywhere instead. The PPC then scales then scales inputs and outputs to get them to floats. The PPC runs at 40MHz, and the coolest part is that it is a circuit controlled by an oscillator. It is very, very deterministic. Combine this with the one hundred or so different type of modules available, and that is why the RIO products that include cRIO can be used for so many tasks in industry and research.

The FPGA has changed a bit year-to-year, but only for bug fixes and to support the 4-slot chassis. At this point FIRST could change it to support new measurements or control, but it isn't possible for teams to change it and still ensure that the safety features are present and working. Imagine that inspection checklist! There are features underway which allow for templating and partial reconfiguration which may allow it to be opened in future years. If a team has an offseason project, I'm pretty sure you could acquire the tools to do FPGA programming.

Greg McKaskle