Quote:
Originally Posted by Kevin Selavko
This is very useful, but it puts an extra strain on our main processor, the C-rio.
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To be clear: when an encoder is connected to the cRIO, the high-speed raw signal from the encoder is processed in the cRIO's FPGA, not the cRIO's Power PC processor. The FPGA is designed to handle these high-frequency signals.
The processor asks the FPGA for a speed and/or position, and uses that to do closed loop control. The processor is plenty fast for that task, if the software architecture is designed correctly.