Quote:
Originally Posted by ajlapp
We do have a strategy to keep loop timing consistent. It involves an internal interrupt used as a "heartbeat." Our lead software engineer is better suited to elaborate. He can jump in on this discussion.
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I'd be interested in that.
I wrote a preemptive rate-monotonic kernel for an Atmega μC in C and assembly 5 years ago back when I was consulting for an automotive smart actuator project. Single stack to conserve memory, and extremely low interrupt latency and context switch overhead. I think it's in production now.