http://www.sal.wisc.edu/PFIS/docs/rs...403-manual.pdf
So you need to understand the difference between the cRIO Module & FPGA and the software layer on top of it.
The cRIO module can detect changes about every 1 microsecond, so unless you're getting one million pulses per second, you're probably not saturating the hardware.
What I expect you're doing is just reading the "current" value of the I/O pin in software, which is probably running every few milliseconds. In that case, if you're getting >100 or >1000 pulses per second (hard to say for sure without knowing the execution speed of your program) you may miss some transitions.
What you could do is set one of the cRIO's hardware counters to read off an I/O pin. I can't remember how to set this up yourself, but the encoder class does this automatically. Essentially, the FPGA counts things in hardware, and the software layer comes along every once in a while and asks "how many pulses have you recorded?" The hardware delivers the number and then resets the counter.