View Single Post
  #31   Spotlight this post!  
Unread 29-01-2013, 11:01
Mr. Lim Mr. Lim is offline
Registered User
AKA: Mr. Lim
no team
Team Role: Leadership
 
Join Date: Jan 2004
Rookie Year: 1998
Location: Toronto, Ontario
Posts: 1,125
Mr. Lim has a reputation beyond reputeMr. Lim has a reputation beyond reputeMr. Lim has a reputation beyond reputeMr. Lim has a reputation beyond reputeMr. Lim has a reputation beyond reputeMr. Lim has a reputation beyond reputeMr. Lim has a reputation beyond reputeMr. Lim has a reputation beyond reputeMr. Lim has a reputation beyond reputeMr. Lim has a reputation beyond reputeMr. Lim has a reputation beyond repute
Re: Best way to measure period between pulses? Counters and FPGA

Quote:
Originally Posted by jhersh View Post
There is a finite resolution on the timing of the pulses. That period is 6.525 us per edge. In your system, does that correspond to 375 RPM? You may want to turn on averaging to improve the resolution (but increase the latency).



Sounds like a coincidence, maybe? Where are you getting 20ms as the refresh period? Just because that's the Driver Station's packet rate?



No. The FPGA only implements method 2.
Thanks a TON Joe!

This post clarified pretty much everything we're seeing.

We WERE hitting the 6.525us timing resolution per edge. That corresponded (coincidentally) with the resolution of 375 RPM we were seeing, at our desired speed.

There'll be a more detailed post, or even a whitepaper once we've sorted everything out, but we've got a really neat solution together involving SetSemiPeriod(true), a mostly white disc with a single small black sector, and an averaging window that holds about 10ms worth of reads at our slowest speed.
__________________
In life, what you give, you keep. What you fail to give, you lose forever...