Quote:
Originally Posted by Ether
The quadrature encoder uses two separate DIO channels. On each channel, there are only 2 edges per cycle (one rising and one falling).
So shouldn't the max be 153K/2 instead of 38K? Or do the two FPGA channels get tied together somehow when you configure them for quadrature decoding, so that each channel is no longer capable of 153K?
|
I got that from an old post on the NI forums from Joe Hershberger.
https://decibel.ni.com/content/message/12541#12541 It probably has to do with quadrature detection for direction. It seems like it would need one clock in each of the 4 states.