Quote:
Originally Posted by apalrd
With a lot of architecture discussions and efficiency improvements, we are currently running all code in a single 10ms RT task with no worries (yet). If we have issue then we can step down to 12ms or 16ms or 20ms.
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Because of this, I tested the current code build on a cRio (4-slot) and the code is using ~38% CPU right now. Since our test chassis (joysticks to 2-pwm drive with servo shifters only) used ~33-34%, but was reading a lot of FPGA IO for display, I'm guessing the overhead (OS + Netcomm) is around 26-30%, and the FPGA transfers use around 3% depending on the number of transfer objects.
Both tests were done with a 10ms RT task at priority 2000 with only the highest-level VI front panel open displaying an iteration timer and RT CPU loads on the front panel. Number is combined CPU load from all priorities.
We've really optimized the architecture and all of the calls to maximize flexibility in calibration and debugging while minimizing the front panel objects on code blocks. This seems to be working really really well.