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Re: US Digital Encoders - How many CPR?
Quote:
Originally Posted by Ether
The quadrature encoder uses two separate DIO channels. On each channel, there are only 2 edges per cycle (one rising and one falling).
So shouldn't the max be 153K/2 instead of 38K? Or do the two FPGA channels get tied together somehow when you configure them for quadrature decoding, so that each channel is no longer capable of 153K?
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My understanding is that the 4 quadrature decoders just use a single counter, counting rising and falling edges on two discrete lines which is why it is 38K max (and keeps track of A and B phase for direction). I do not believe it use two separate counters for each DIO channel.
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Last edited by NotInControl : 01-02-2013 at 14:01.
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