Quote:
Originally Posted by NotInControl
My understanding is that the 4 quadrature decoders just use a single counter, counting rising and falling edges on two discrete lines which is why it is 38K max (and keeps track of A and B phase for direction). I do not believe it use two separate counters for each DIO channel.
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No. A quadrature encoder uses 2 DIO channels. Each channel gets polled synchronously by the FPGA at 153KHz. Each channel counts its 720 edges at 153Khz.
But the encoder will not work if the elapsed time between rising edge on channel A and rising edge on channel B (or vice versa) exceeds 1/153KHz seconds, because the FPGA won't be able to tell which came first. That's where the 38K limit comes from.