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Originally Posted by sst.thad
The is a function you can use to set what the FPGA sees as stopped. its the setMinRate function.
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Quote:
Originally Posted by Joe Ross
In the Encoder class it's called setMinRate, in the Counter class it's called setMaxPeriod.
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Sounds like the answer to our problems.
I imagine that we don't want to use the stalled feature at all. Is there a downside to setting the max period to a high value? e.g. 6 seconds period is equivalent to 10 RPM. This would seem safe at any reasonably low speeds. Is there any functionality trade off to setting a high max period?