Quote:
Originally Posted by Bunniy
here
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I would recommend you let the FPGA compute the period in hardware with its 153KHz sampling and 1MHz clock (like Mark showed), instead of doing it in software. There's no need for the IIR filter if you set the proper size for the FPGA's sample ring buffer. If you you need to avoid large current spikes at startup (perhaps to prevent Jags from cutting out), try speed-based throttle limiting instead of time-based slew rate. I would avoid using a Jag for bang-bang because of the startup current spike.