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Unread 14-08-2013, 11:32
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Re: NI Week Athena Announcement and Q&A Panel

Speaking of boot times, any official input on boot times? Download times? Compile times? Any times? Any time requirements/specs, if the development isn't finished yet?

My work projects (all on 180-240mhz MPC5600 PowerPC's) have a requirement to boot and be ready to synchronize in under 300ms from chip power on. The requirement was the same for the 56mhz MPC500's and older processors, and they also met it.

I don't know if there is any time requirement at all on the current system, and it seems like there just plain isn't (crazy!). VxWorks currently boots in a few seconds (which is very reasonable), the rest is all Netcomm and user code. There is a lot of inefficiency in the user code init libraries (at least in LV, for example the encoder open block reads/writes the same config register and converts units 4x times) too. But a lot of it is still in Netcomm, and I've been told it's because it has to load an FPGA image to read the ADC cals, then unload that image and load the real FPGA image. I would gladly sacrifice a bit of FPGA functionality (for example two counter channels, or the DIO PWM, or DMA) to fit the ADC cal reading in the main FPGA image.

The Vex guys can boot a Cortex and user code and establish radio link in ~15s. The PIC-based IFI would boot and establish radio link in 5s. Why are we sitting around a minute? And getting worse every year?

As for size, it's not too much smaller than an IFI RC. Very similar in size.
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