[Kevin Sevcik]

The Labview FRC codebase has approximately zero control over the FPGA on the cRIO. The FPGA image is pre-compiled by the wizards that create the WPILib FRC framework, and all Labview/C++/Java code merely interfaces with the FPGA through DMA calls and such. So no, the Real Time timing VIs don't have much of anything to do with the FPGA and wouldn't off-load any processing from the CPU to the FPGA. They are much higher accuracy and more deterministic than the standard "Wait (ms)" function, however, and that obviously carries a higher CPU cost with it.