[Greg McKaskle]

To reenforce what Kevin said .. the cRIO product allows for a combination of hard and soft realtime operation. But for FRC, that division has already been defined, and compiled into the image. Until the FPGA tools better support partial reconfiguration, it isn't really feasible to allow for FPGA modification and ensure safety of outputs.

So in the RT palette, the timers and such are referring to realtime implementation of those concepts. These will attempt to minimize latency and jitter at the expense of efficiency. They are more likely to use spin-lock instead of messaging or signaling. They are more likely to run at elevated priorities.

What I'd suggest is identifying the elements of your code that are causing your CPU usage to be high. They may not be the same as the ones causing the jitter in timing. It would also be helpful for you to describe your usage of CAN. What CAN messages are being sent to how many controllers? You may also want to measure just the CAN nodes and see if they are the big pole in the tent.

Greg McKaskle