Quote:
Originally Posted by compwiztobe
What if the FPGA cannot keep up with all of the counts it would be averaging at 1x? Does it still properly count every 4th tick, even though the 3 in between go by too quickly? And then adds in the extra samples (and direction sensing) provided 3 intermediate ticks, provided they are slow enough to capture? Sort of nitpicking...
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All that matters is the edge that it is looking for at 1x does not exceed the digital clock rate (It will count and handle direction correctly, but will have horrible rate noise). It doesn't matter if the other edges happen too fast, because it will latch the values on the digital clock.