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Re: How to use FTC hi-tech motor controllor on FRC
It looks like the cRIO/fpga is not keeping the SCL line low long enough during reads and the slave isn't stretching the clock.
The clock problem is fairly clear to see if you look at the capture in the prior post.
Anyone know if the specs/API to the FPGA is available or the VHDL (or other source) for it?
I'd like to fix the library if possible before I move on to a hardware solution.
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