Quote:
Originally Posted by Joe Ross
Semi-period mode is not ideal for this sensor, because the data sheet recommends using the duty cycle.
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Good catch (paragraph 8.2 of the AS5145B datasheet).
The same holds true for the
US Digital MA3:
Quote:
Originally Posted by Ether
Decoding PWM duty cycle (which is the datasheet-recommended way to decode the PWM signal for the MA3) would require measuring both the pulse width and the period (or the associated non-pulse width) for the same cycle. I don't think the 2014 FPGA is programmed to do that.
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Quote:
Originally Posted by Ether
I've heard the FPGA sampling frequency will be bumped up from ~153KHz (in 2014) to ~1MHz (in 2015). Maybe the FPGA will be programmed in 2015 to read duty cycle (detect and report consecutive rising-to-falling and falling-to-rising edge pairs). If so, you could decode the PWM quite accurately using that.
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Do you know if there are any plans to add duty cycle decoding to FPGA?