Quote:
Originally Posted by asid61
Runs at 100MHz each for 4 cores, but I need to do port read/write tests. It should only take one clock tick per reading, but now I'm wondering how I would report results without losing some functionality. I could just add another XMOS and run encoder readings on 4 cores.
|
Really? That's a pretty fancy chip.
On the Cortex-M3, it takes 3 cycles to access the AHB bus on the fast GPIO, and on older generation chips, slow GPIO would take north of 10 cycles (if I remember right).
Peripheral accesses tend to be pretty slow, even on embedded chips. CAN receiving code that I have used on a i7 over PCI takes a very long time. The CPU busy waits while that is happening. The result is that it takes about 1 core to read CAN messages (!).