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Originally Posted by philso
Thanks for your input, Scott. It is interesting to get your perspective as a power electronics professional.
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Ha ha.. I have to LOL on that comment. I'd hardly give myself that attribute. I'm an embedded semiconductor kind of guy (architecture/hardware/software). My experience with power electronics is due to my being employed at Luminary Micro some years ago who built microcontrollers (MCUs) for use in applications such as motor control. Specifically, you can blame me for Jaguar (he ducks as rotten tomatoes are hurled in his direction).
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If changing the refresh time will make the MOSFETs saturate properly, they could update the firmware in the original and improve it's performance too.
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To be clear, I wasn't suggesting that the Cboot voltage was decaying and affecting the Vgs level on the high-side MOSFETs. Actually, the scenario I was thinking about was that the they were over refreshing and therefore incurring an un-necessary drop in efficiency.
The Cboot cap is charged up when the connected terminal (M+ or M-, there is one Cboot for each) is driven low (the low-side MOSFET is turned on). The cap charges through a diode and current limiting resistor. The Cboot charge time is therefore 3-5 RCboot times. But, the firmware in the MCU controls the timing. If you're curious, check out the Jaguar's published schematics.
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The stated change to make the "B" version was to remove the under-voltage lockout feature which should have no effect on how the MOSFET gates are controlled during "normal" operation.
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Yeah, the under voltage would be the VBUS voltage reduced by a divider circuit to an ADC input, being sampled by firmware, and setting a different trip point value or updated software-based filtering to activate exceptional processing. Also a firmware change (likely).
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It would be interesting to see if anyone who has an SD540 or SD540B can put a scope probe on the output. It is possible that the SD540B uses a switching frequency lower than 32.25 kHz to cut the switching losses in half. I would also be interested to see how clean the output waveforms are. I have had to fix inverters where poor internal layout led to excessive voltage surges which led the designers to greatly increase the gate resistance (increasing switching losses and allowing the Miller Capacitance to cause oscillations).
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Agreed. From a pure curiosity perspective, I'd like to see this done for all motor controllers. It would provide some insight into the real power loss (IRds(on)). It is easy to see: connect small resistive load across M+/M-, connect scope to M+ and V-(ground), set output to 100% forward, measure duty cycle and frequency on scope.
Scott