Quote:
Originally Posted by Thad House
Joe, do you know exactly what the pulses per second rating for encoders/counters in the FPGA is? I remember that the cRIO was right around 40,000, and I remember hearing that the RoboRIO was in the realm of 100,000, but I would like to know for sure. It would also be nice to have this documented somewhere if possible.
EDIT: Nevermind. I didn't see the 25ns number above. Does that mean that that the RoboRIO can take 40,000,000 edge to edge pulses per second, or am I screwing my math up somewhere.
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If you look at "roboRIO Specifications" linked from
here, in the Digital I/O section on page 4, it references "minimum pulse width". That's the hardware limit. The FPGA implementation uses a 40 MHz clock as the timebase to run the decoder logic and the I/O logic. That means the FPGA is the limiting factor by a small margin. There are complications (discussed earlier) with respect to the sampling and ensuring no two edges are detected in the same sample period. To ensure that is avoided, divide the rate by 2. That means 20,000,000 edges per second should be guaranteed to decode. That edge rate would mean 5,000,000 rising edges on the A encoder output per second (assuming very small phase error in your encoder both A to B and rising to falling).
Quote:
Originally Posted by Thad House
That number just seems incredibly high, but I could see it being that high.
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Quote:
Originally Posted by jhersh
...the roboRIO's vastly faster DIO...
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It is incredibly high... by comparison to the previous system anyway.