Quote:
Originally Posted by Jared Russell
I verified last night that I was able to use a pair of counters (one in semi-period mode capturing the rising-to-falling period, and one in normal mode for capturing rising-to-rising period) to measure the duty cycle of the 12-bit PWM MA3.
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When you do it that way, how do you ask the FPGA to give you the rising-falling and rising-rising from the same cycle?