Quote:
Originally Posted by wireties
Thanks! I might hit you up for some help. All in Verilog, nothing in VHDL?
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I can't remember. Might have been VDHL. If you dig through the documentation, you can eventually find instructions on how to build a new image, or give me a holler. It took me a solid day to figure it all out. (If you need a prompt response, I'm waaay faster on gchat).