[Max Lobovsky]

Originally Posted by Joe Johnson

I want to say right away that I am not a EE (though I sometimes play one on TV ;-).

If you want specific chips, I have found the following from Digi-key. I believe they will work, but it is possible you may need an inverter here or a NOR gate there to get things to work exactly as you want.

As to the 8 bit up/down counter:
SN74ALS867ADW


http://focus.ti.com/lit/ds/sdas115c/sdas115c.pdf

As to an 8 bit parallel load shift register:
74F676

http://www.fairchildsemi.com/ds/74/74F676.pdf

You can have the clock for the counter be driven by one channel of the encoder, the other channel of the encoder is tied to the up/dn pin of the counter.

The CPU drives the "parallel load" mode of the shift register and then shift in the bits to the its input pins.

You can daisy chain the 676's to have the data look like one long register.

You can also cascade the counters if you need to have more counts than an 8 bit number can hold.

Alternatively, you can also reset the counters after you read them so that you can just accumulate the total count inside your CPU. You run the risk potential of missing a count when you reset the counters if you are not careful, but depending on your application, this may or may not be a big deal. With some clever circuitry and/or software you can avoid this problem but this is more than I want to get into here.


I don't know if this helps, but it should be a good start.

Joe J.

P.S. I have used the 676 before so I can vouch for it with first hand knowledge. However, I have not used the 867 before -- I have always had some other 4 bit counters hanging around the office that I could cascaded into whatever size counter I needed. From what you are talking about, I suppose you will need more than 8 bits perhaps 16 bits. This gets tedious with 4 bit counters so I suggested an 8 bit version. Looking at the data sheets though I am pretty sure that it will work out for your application -- perhaps others have favorites they are used to using that they can vouch for from personal experience.

So basically, the parrallel outputs of the counter are connected to the parrallel inputs of the shift register. The shift register is put permanantly into parallel load mode (Mode is high) Then, to read the shift register, the CPU has a digital IO pin connected to the CP (clock pulse) pin which it pulses, then checks serial output, and repeats to get all 8/16 bits of the counter? I'm not sure if the proper way to do this is to actually have a common clock or something like that, but this seems to be correct, too.

I wrote up some code to do what i think you're saying:

 
char encVel()
{ 
char encVel;
for(int i = 1; i<9; i++)
{
/*set clock to shift register high*/
shiftClkA = 1;
/*read the current bit of the shift register encVel*/
encVel |= serialInput<<i
 
/*set clock back*/
shiftClkA=0;
 
}
/*reset counter*/
counterResetA = 1;
counterResetA = 0;
return encVel;
}