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Originally Posted by Kevin Watson
Alan,
The simplest way to do this is with a D-type flip-flop (e.g., 74ACT74, 74HCT74, 74LS74, etc.). The encoder's phase-A signal goes to the the clock input and the RC interrupt input. The phase-B signal goes to the flip-flop's D input and the Q output goes to the RC digital input formally used by the phase-B signal. I prototyped this circuit and saw a pretty dramatic increase in the maximum count rate that the RC could handle.
-Kevin
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Three quick questions:
1) Must interrupts 3-6 be enabled/disabled as a package? i.e. you cannot ONLY enable 3, but not 4-6? I am using two encoders and the Hall Effect sensor, and need only 3 interrupts, and would rather not have to enable 6 of them.
2) If Q1 is true, and we enable 3-6, should we move the phase-B signal on I/O 6 to 7 in order to avoid unnecessary interrupts?
3) Does phase stretching circuit described in the threads above allow a faster count rate because it prevents the phase-B state from changing (to the wrong state) before the interrupt is serviced?
I know some of these should be pretty obvious, but Team 188 is running the Grayhill 63R256 encoders, and our count rates are pretty high. I'm hoping to stave off any interrupt issues that might arise =).
-SlimBoJones...