Thread: FRC hardware design
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Unread 22-08-2005, 13:59
Gdeaver Gdeaver is offline
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Re: FRC hardware design
I'm suggesting that having 2 pic 18's and the interrupt for them to talk adds complications. Having 1 pic 18 and a pic 16or two on an expandable async bus would be less complex. The main processor would have a senddata getdata function and a set-pwm function. Off loading the PWM from the pic 18's would eliminate the critical timing that is needed in the current controller. As for cost, aren't pic 18's to pic16's about 1 to 3. I would rather send a couple high level commands to a intelligent motor coproc than have to fit the pid in the current FRC and worry about conflicts with a gyro, accelerometer, other time critical sensing.