Quote:
Originally Posted by dcbrown
All the io lines are noise filtered with RC networks. The io lines that support analog inputs being the most heavily filtered( about 5x the normal digital io lines), the interrupt io pins being the least filtered (about .1x). Be aware that:
MYSPI_CLK = 1;
mask >>= 1;
MYSPI_CLK = 0;
would probably work ok in a bare PIC18F environment, but with the digital lines spec'd to max 50Khz response time (20us?) the above clock pulse will never show up at the IFI controller pin. You'd likely need to add lots of nop delay to wait for the rise time on the pin and also filter it through a schottky or some other type of buffer to clean up the slow rise "pulse" into a real clock edge.
http://www.ifirobotics.com/rc.shtml#Specifications
http://www.ifirobotics.com/docs/anal...al--i-o-rc.pdf |
Good catch.
Moving the bit-banged SPI lines to I/O 1-6 would certainly speed things up, but also recognize that the output lines have no series R between the port pin and the capacitor, so now the rate of rise/fall is determined primarily by the CPU's output gate drive capability which appears to be on the order of 230 ohms sourcing and 70 ohms sinking.
I'm estimating the equivilant output resistance by taking the specified worst case voltage drop at a rated output current for the port pins and calculating the equivilant resistance.
So 1T would be about 230ns right?
So on I/O lines 7-18, with the 10nF cap hanging right on the port pin, 1T would be 2.3us.
Clearly if the SPI port needed to bring data IN, then yes I would limit the input data rate to 40kHz on I/O lines 7-18, and maybe 300kHz on I/O lines 1-6. Assumes 3T (95%) settling times.
For an output only configuration, then rates of 140kHz for I/O 7-18 and 1.45MHz for I/O 1-6 would probably be ok.
I would agree that some circumstances may necessitate the need for a schottky gate might be necessary, but lacking any additional information its hard to comment beyond that.
Along those lines, no matter what the external part or parts may be, that the interconnecting lines should be kept as short as possible, and that the target system either share the same 5V supply, or at least provide a means of protecting against differences between sepearately derived 5V supplies. The input impedance of the IFI appears to be high enough to prevent damage if one system was unpowered, it is still low enough that one could potentially be partially powered from the other via the protection clamping diodes.
Thanks,