[comphappy]

WOW, this is what i wanted, but not at all what I expected. How do they expect me to wait until next year for this. Any one else excited about the FPGA possibilities? I hope we will be able to do the verlog an VHDL with out too much abstraction. I guess its time to roll out the grants and start writing.

Teaching this to the rest of the team and learning it my self is going to be a challenge more so then last year, I just hope I wont have to run build again this year. This could be a year where the programing makes or breaks it for teams.

This system is going to up the cool factor when showing it off the companies, it just looks more cutting edge with the wires and stuff hanging out like they do.

Did i say FPGA?
FPGA