[Greg McKaskle]

The NI I/O model depends on the HW target, but in this case the FPGA and the PPC use a memory mapped register set. Instead of the driver kit seen above, you'd see something equivalent to an

NI_RIO_PEEK(FPGARef, address, &result);

The FPGARef is the result of an early Open that loads and/or connects to an FPGA image.

Then because some of the access would be difficult, there is a layer that supports critical section exclusion and provides cleaner C datatypes. This layer of C++ objects is generated with the FPGA image, and that is what WPI will link against.

Greg McKaskle