Quote:
Originally Posted by Greg McKaskle
The NI I/O model depends on the HW target, but in this case the FPGA and the PPC use a memory mapped register set. Instead of the driver kit seen above, you'd see something equivalent to an
NI_RIO_PEEK(FPGARef, address, &result);
The FPGARef is the result of an early Open that loads and/or connects to an FPGA image.
Then because some of the access would be difficult, there is a layer that supports critical section exclusion and provides cleaner C datatypes. This layer of C++ objects is generated with the FPGA image, and that is what WPI will link against.
Greg McKaskle
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So NI_RIO_PEEK and NI_RIO_POKE (assumption) would work within kernel applications/tasks, but what about RTPs? Since opens are not traditionally shared across the RTP/kernel interface could RTPs do their own open on the FPGA image or will this type of macro call only work inside the kernel?
Is there a technical architecture overview document for the FPGA and NI I/O modules - essentially similar to VxWorks component API manuals? Trying to find any real tech information on this platform has been particularly frustrating. Especially since this is NOT a new platform. I don't need to know the particulars of how the FPGA/IO interface will be set up for FRC, but it would help immensely to know what a typical engineer recieves in terms of documentation, software templates, and information when they buy an cRIO IO module.