Quote:
Originally Posted by JesseK
The good news is, if they fix any beta bugs during a competition it will take mere minutes to implement and mere seconds to upload over the wireless to our bots  Hopefully FIRST is thinking about this framework and will keep a special upload port ready for such bug fixes.
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Minutes is probably a little optimistic. For a team with a laptop that just meets LabVIEW requirements, I'd guess 10-15 minutes, since a fix to some base level code is going to invalidate a fair number of things. And the field controller... That's going to be complicated enough that any fixes would probably be done over lunch.
Quote:
Originally Posted by Alan Anderson
It's possible that such bugs would be in the FPGA portion of the system. Fixing them could take a whole lot longer than you expect. The equivalent of the code/compile/load/test cycle for VHDL is often measured in hours.
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I'll note that on a 1M gate NI FPGA, I managed to implement the forward kinematics for a 3-DoF rotational joint device, X-Y-Z PD loops, and the transverse Jacobian to take those XYZ forces back into joint space, with lookup tables for all the trig functions. It only took 30 minutes to compile on my 2.0 GHz dual-core laptop. And if I changed some of my built in constants for joint lengths, it wouldn't fit on the FPGA anymore. So while I don't think it'll take hours to recompile the safety, PWM, and (hopefully) encoder logic on the FPGAs, it's definitely not going to be mere minutes.