Quote:
Originally Posted by dcbrown
So for example, a quad encoder ISR on the PIC that had phase A/B input and tracked a count would be implemented within the FPGA and could have the added value of dealing with all four phase transitions on multiple encoders. Each encoder would have its own dedicated FGPA hardware to process it. The resulting exported data would be a h/w register with the current count.
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This is assuming, of course, that all this functionality is actually implemented on the FPGA for us. I'm not entirely certain that's a given. Of course, if it's not on the FPGA and we aren't allowed to implement it ourselves, I'm going to feel pretty darned silly still doing quadrature encoder counting using interrupts. Actually I'm going to feel pretty annoyed even if they implement the encoder logic on the FPGA for us, since it's pretty unlikely ever team is going to need the exact same number of encoders. Seeing as how a mechanum system with two feedback controlled joints would potentially need 3 times the interfaces as a two wheeled kit bot.