Quote:
Originally Posted by Daniel_LaFleur
From the looks of it, we will be using the DIO ports to generate PWM signals (Gosh, I hope there is no latency in the bus).
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From the looks of the
digital side car, all PWM outs are connected to a chip labeled U2, so that should be the final stage of the PWM generation (or it could just be a buffer). What signals the FPGA and DIO modules send to drive that IC, I am not sure.